The present disclosure relates generally to semiconductor device manufacturing techniques and, more particularly, to implementing three-dimensional integration of multiple integrated circuit (IC) devices using alignment via/dielectric bonding first and through via formation last.
The packaging density in electronic industry continuously increases in order to accommodate more electronic devices into a package. In this regard, three-dimensional (3D) wafer-to-wafer stacking technology substantially contributes to the device integration process. Typically, a semiconductor wafer includes several layers of integrated circuitry (e.g., processors, programmable devices, memory devices, etc.) built on a silicon substrate. A top layer of the wafer may be connected to a bottom layer of the wafer by through-silicon interconnects or vias. In order to form a 3D wafer stack, two or more wafers are placed on top of one other and bonded.
3D wafer stacking technology offers a number of potential benefits, including, for example, improved form factors, lower costs, enhanced performance, and greater integration through system-on-chip (SOC) solutions. In addition, the 3D wafer stacking technology may provide other functionality to the chip. For instance, after being formed, the 3D wafer stack may be diced into stacked dies or chips, with each stacked chip having multiple tiers (i.e., layers) of integrated circuitry. SOC architectures formed by 3D wafer stacking can enable high bandwidth connectivity of products such as, for example, logic circuitry and dynamic random access memory (DRAM), that otherwise have incompatible process flows. At present, there are many applications for 3D wafer stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, and other SOC solutions.